With COVID-19, the formation of telecommuting, online meetings, and online education habits has accelerated the digital transformation of several industries and has also promoted technological updates in Network Communications, AI, Data Storage, and Cloud Services from the side. On the HW infrastructure side, the Semiconductor industry is expanding capacity while aggressively upgrading processes to increase computational and data handling capabilities. The key demand in 2023 for semiconductors will be driven by some of the applications below:
Going 5G: The long promised 5G network that would make the world wireless has finally arrived, and the applications go way beyond telecommunications: customized private 5G networks will bring high-speed, high-capacity, low-latency connectivity to indoors industry and government networks. The increase in 5G penetration in new smartphones will contribute to the high demand for new chips, especially for mmWave frontends and IoT devices.
Automotive: For the semiconductor industry car technology is the new playground. Radar chips, sensor, safety, and more silicon are put into use in new cars. Both startup and large IDM are putting together ICs and solution for electrical cars as we speak.
Artificial Intelligence: AI, machine learning and data analyses is now present in almost any high-end smart device. The recent advancements in AI hardware and acceleration will demand a great number of specialized ASICs in 2023, promising to add more heat to the chip market.
Cloud Computing: The demand for servers is likely going to increase in 2023. The category can expect some interesting innovations, as Intel and Google recently announced their collaboration in the development of the Mount Evans, an ASIC optimized for cloud infrastructure, and Alibaba launched their new server chip, the Yitian 710.
At Service Ventures, we expect the following macro industry and technology trends to take dominate in the semiconductor industry in 2023, driven by the above application demands.
1/ Mass Production of 3nm Process Node
In terms of semiconductor cutting-edge manufacturing processes, it seems the 4nm process will become the focus of Samsung's promotion for the near future. In 2021, TSMC also released the news that 3nm N3 process might be delayed, and hence the coming few years may become the years of the 4nm process. Although the fastest chip using TSMC's N3 process will probably need to wait until the first quarter of 2023, but the N3 process mass production may soon be realized with Samsung 3nm Gate-All-Around (GAA) coming maybe a little later than TSMC N3. Samsung started to use GAA FET at the 3nm node as the focus, but it failed to follow the timing to advance as scheduled. Based on Samsung's current public data, its earliest 3nm process may be subject to greater uncertainty at the technical level. Intel on the other hand is unable to catch up to this node. TSMC N3 will continue to maintain its dominant market position and has a significant lead over the other two rivals for the time being. Intel 20A process is expected to arrive in the first half of 2024. Intel 18A may be seen in the second half of 2025. Intel's determination to return to technology leadership at these two nodes is quite strong. Samsung is expected to mass produce 2nm process in the second half of 2025.
2/ DDR5 Memory will Be a Game Changer
Memory bandwidth is growing much faster than processor performance. In 2020, to address the performance and power challenges facing a wide range of applications from client systems to high-performance servers, the Solid State Technology Council released the final specifications for the next-generation mainstream memory standard DDR5 SDRAM. It describes DDR5 as a "revolutionary" memory architecture and believes that its emergence marks the industry's imminent transition to DDR5 dual inline memory modules (DIMMs). DDR5 is faster than the already fast DDR4. Compared to DDR4 memory's maximum 3.2Gbps transfer speed at 1.6GHz clock frequency, the new DDR5 memory reaches a maximum transfer rate of 6.4Gbps and synchronizes the power supply voltage from DDR4's 1.2V to 1.1V, further enhancing the memory's energy efficiency performance. Unlike previous iterations of the product, which focused primarily on how to reduce power consumption and prioritized PCs as applications, the industry generally believes that DDR5 will follow DDR4's lead and take the lead in data centers. Currently, global storage giants such as Samsung, SK Hynix, and Micron have announced their respective mass production and commercial timelines for DDR5 products. However, DDR5 will not come to market overnight and will require strong support from the ecosystem, including system and chip service providers, channel vendors, cloud service providers, and original equipment manufacturers. We believe, in 2023, DDR5 will be widely adopted in mainstream markets such as cell phones, notebooks, and PCs, with shipments significantly exceeding DDR4, completing a rapid transition between the two technologies.
3/ DPU Market will Expand and Become Specialized
In the early years of data centers, there was a term called "data center tax", i.e., the servers purchased many-core CPUs. But during usage, some of these cores were used to do virtual networking, security functions, storage management, virtualization tasks, and other needed work. When these tasks become increasingly complex, the DPU becomes a necessity. Just as there are GPUs for graphics computing and NPUs for AI computing, DPUs are a product of the rise of dedicated computing in this era. The DPU became popular near the end of 2020, NVIDIA's acquisition of the Israeli company Mellanox, which coined the term "DPU", and the startup Fungible's big promotion of the name DPU in the same year. DPU is essentially the evolution of smartNIC. The work of DPU includes offloading the original CPU overhead, storage, security services, and other activities; Hypervisor management to do isolation, Virtualization implementation to further accelerate the cross-node data processing. But their specific implementation depends upon the roles they play. Intel's IPU is also a DPU, it is a bit different from the NVIDIA DPU in terms of responsibilities and work bias. We believe there is a possibility that the DPU market might be segmented.
4/ Storage and Compute Integration will be An Industry Norm
When data is extracted from the memory outside the processing unit, the handling time is often hundreds or thousands of times longer than the computing time, and the energy consumption of the whole process is roughly between 60% and 90%, which is very inefficient. With a flood of data, problems such as slow data transfer and high energy consumption have become computational bottlenecks. Moore's law is close to the limit, and the von Neumann architecture, which is limited by the storage wall, can no longer meet the needs of this era in terms of computing power enhancement. But with the advancement of the chip manufacturing process and the development of artificial intelligence (AI) applications in recent years, processors are becoming more powerful, faster, and have more storage capacity. There are many novel non-von Neumann approaches to make heavy data compute more efficient. These non-von Neumann architectures include low-voltage sub-threshold digital logic ASICs, neuromorphic computing, and analog computing, with memory-compute integration being the most direct and efficient. This is a new type of computing architecture that does two- and three-dimensional matrix multiplication operations rather than optimizing on traditional logical computing units. This can theoretically eliminate the delay and power consumption of data transfer, hundreds of times more efficient AI computing and reduce costs, so it is particularly suitable for neural networks.
5/ RISC-V Architecture will Enter High Performance Computing (HPC)
Designing a new microprocessor is hard and requires many professionals with different specialties working in synergy. When a chip designer wants to create a new microcontroller or SoC, he selects the best suited processor architecture in the market, pays the license fee and plugs the IP core into his design. Proprietary instruction set architectures (ISA), such as Intel and ARM, dominated the market for several years. To sustain technological dominance, these companies fight to keep their design secrets safe, so the reasoning behind any design decision remains hidden. Although this approach is understandable from a business perspective, it makes it difficult for early-stage companies to put new processors into the market due to the costly IP fees, which in turns reduce competition and innovation.
In this scenario, the RISC-V architecture was developed. The RISC-V is an open-source ISA was developed at the University of Berkeley, California 10 years ago, based on the reduced instruction set principles. It is completely open-source and free to use, which embraces small businesses and new developers without requiring fees to use. The open-source nature allows the development of a community of different contributors, kickstarting innovation and optimization. Although still shy in comparison with the proprietary giants, the RISC-V should face an exponential growth in market revenue in the next few years.
RISC-V has now become the mainstream opensource microprocessor Instruction Set Architecture (ISA). But its main application currently is limited to the field of embedded systems and microcontrollers, especially the IoT market. We believe this open-source microprocessor architecture can match the HPC capabilities of X86 and ARM ISAs. From chip giants, fabless startups to microprocessor kernel IP developers are trying to introduce RISC-V to HPC applications such as AI, 5G, and other compute heavy server workloads. SiFive's Performance Series P550 is a high-performance RISC-V kernel, designed for Network processing, Edge computing, Autonomous machine, 5G base station, Virtual/Enhancement reality. It uses RISC-V ISA, 13-level flow line, and the quad-core has 4MB of three-level cache, main frequency 2.4 GHz. The occupied space of the quad-core P550 cluster is roughly equivalent to a single Cortex-A75. Intel will use the P550 cores in its 7nm Horse Creek platform, and by combining Intel interface IPs such as DDR and PCIe with SiFive's P550, Horse Creek will provide valuable and scalable development tools for high-end RISC-V applications. Esperanto, another fabless design startup, has introduced an AI chip with more than 1,000 integrated RISC-V cores designed for AI reasoning in data centers. Using TSMC's 7nm process and integrating 24 billion transistors, the chip includes 1088 high-performance 64-bit RISC-V ordered cores (and each core comes with a vector/tensor unit); 4 high-performance 64-bit RISC-V disordered cores; and over 160MB of on-chip SRAM. The chip's peak computing performance of 100-200 TOPS for ML inference, and its operating power consumption is less than 20W. Key players that are already using RISC-V designs include Samsung, Microchip, Google, Nvidia and Qualcomm. Although the future of RISC-V in the industry is still uncertain, the popularization is inevitable in 2023.
6/ Chiplets
A prediction made by Gordon Moore in 1965, based purely on empirical observation, determines that the maximum transistor density inside a chip, and hence the computing power, doubles every two years. He predicted it so well that it became a law, that lived strong and well until recently. The conventional way of manufacturing chips, which relied on cramming as much computing and graphics capabilities into smaller chips, is reaching some limitations. Chips are becoming harder to manufacture, which has slowed down advances in chip technology. Director of the Microsystems Technology Office of DARPA, Robert Colwell, predicted 8 years ago that Moore’s Law wouldn’t see the light of 2022, stopping probably at the 7 or 5nm node. TSMC announced the 3nm in 2020, overcoming the 5nm performance limitations by using the gate-all-around (GAA) technology. TSMC’s plan could give at least one last breath to Moore’s prediction. Samsung also expects to produce the 3nm node soon. Besides the physical limitation of brute-force transistor shrinkage, the cost and time necessary to manufacture tech-leading nodes is becoming more and more unpractical.
So major chipmakers are now taking a new approach with chiplets, which are modules that can be pieced together to construct a chip. Chiplets are like Lego blocks – a customer can mix and match chiplets of their own to build a custom chip. Chiplets divide a single die into several small dies that work together in an optimized package. 3D chiplets go one step further, and stack multiple chiplets on top of each other. Both Intel and AMD are planning to implement chiplets in the next generation of processors, with AMD having the upper hand by using 3D stacking combined with the 7nm node in collaboration with TSMC.
At Service Ventures, we believe that the chiplet approach will be favored over conventional monolithic IC designs as it provides a way to customize and manufacture chips for industries outside tech and consumer electronics. If a customer wants to build a chip for artificial intelligence, they can piece together chiplets that includes a CPU, a graphics processor, and an artificial intelligence accelerator, and send it over to a chip manufacturer like Intel and TSMC for fabrication. Hardware companies such as AMD and Apple are already using the chiplet approach for PCs and servers. Chips are emerging as building blocks for industries like automotive, and major auto companies in the last two years had to shut down production of cars due to a shortage of chips. According to Pat Gelsinger, CEO of Intel, chips will be for the next few decades what oil and gas was to the world over the last 50 years. Data will travel between chiplets over very short distances, which is different from conventional dies where signaling happens over longer electrical distances. The energy consumptions on chiplets however will need to be lower per bit, and efficiency needs to be achieved on the area, bandwidth, and other metrics.
We are keeping an eye on some of those trends and looking forward to seeing how they evolve under the many uncertain macro factors we cyrrent have.
/Service Ventures Team
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